FIG. 1 diagrammatically illustrates a conventional CAN (Controller Area Network) receiver arrangement. (See also the International Standard, ISO 11898-1:2003(E).) A transceiver (XCVR) 12 includes a receiver portion that receives signaling from the CAN bus 15, and samples the signaling in accordance with a sampling interval defined by the frequency of a sampling clock 11 that is received at an input CLK. As a result of the sampling operation, the transceiver captures a stream of bit samples for a CAN frame that has been transmitted on the bus 15. The stream of bit samples is provided at 16 to a frame processor 13 that uses the bit samples to decode the CAN frame. Among other tasks, the frame processor 13 checks for and removes bits that were “stuffed” into the frame at the transmitter (also called de-stuffing), and performs a cyclic redundancy code (CRC) check for the frame. Based on the de-stuffing and CRC checking, the frame processor 13 decides whether or not the frame has been decoded successfully.
Due to various well-known characteristics of the CAN frame transmission protocol, the sampling clock 11 must typically have about a +/−2% frequency tolerance to ensure that the frame is sampled and decoded successfully. This level of sample clock accuracy typically requires either a crystal oscillator or post fabrication trimming, both of which disadvantageously increase manufacturing costs.
It is desirable in view of the foregoing to provide for compensating an insufficiently accurate sample clock in a communication receiver (such as, e.g., a CAN receiver).